Field of the Invention
The present invention relates in general to integrated circuits. In one aspect, the present invention relates to stacked semiconductor die devices and a method for designing and manufacturing same.
Description of the Related Art
The semiconductor industry has traditionally pursued higher density of circuits (e.g., analog, memory, CPU, graphics, etc.) and electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) by reducing the required two-dimensional (2D) chip area for integrated circuit components. However, there is increasing interest in developing three-dimensional (3D) integrated circuits to achieve higher device density by bonding two or more layers of circuit substrates or wafers into a stacked die architecture. 3D packaging architectures, including stacked die architectures, can provide higher circuit density over 2D packaging architectures, and can also improve performance by reducing interconnect distances between circuits located on different levels of the stacked die. For example, with 2D systems-on-chip (SoC) integration where the memory is surrounded by logic circuits, system performance in terms of memory bandwidth is limited by a number of factors, such as the length of long interconnects, the number of interface pads on a mother die, etc. But with 3D integration, the physical distance between the memory and the logic circuits is reduced. However, there are design challenges presented when large numbers of devices are densely packed into stacked device layers, such as heat removal, power delivery, and fabrication processing.
Accordingly, a need exists for an improved system for designing and manufacturing stacked semiconductor die devices which addresses various problems in the art that have been discovered by the above-named inventor where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.